Adaptive multi-bit delta and sigma-delta modulation

ABSTRACT

An adaptive multi-bit delta and sigma-delta modulation and demodulation technique, wherein a one-bit modulator generates a binary output signal from an analog input signal and a multi-bit adapter for generating a scaling signal for scaling a step-size of the sigma-delta modulator.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(e) to U.S.Provisional Patent Application No. 60/418,644, filed Oct. 15, 2002, byAli H. Sayed and Mansour A. Aldajani, entitled “ADAPTIVE MULTI-BIT DELTAAND SIGMA-DELTA MODULATION,” which application is incorporated byreference herein.

This application is a continuation-in-part of and commonly-assigned U.S.patent application Ser. No. 10/332,750, filed on Jan. 13, 2003, byMansour A. Aldajani and Ali H. Sayed, entitled “ADAPTIVE SIGMA-DELTAMODULATION WITH IMPROVED DYNAMIC RANGE,” now U.S. Pat. No. 7,073,113,issued Jul. 4, 2006, which application claims priority to co-pending andcommonly-assigned International Application No. PCT/US01/22193, filed onJul. 13, 2001, by Mansour A. Aldajani and Ali H. Sayed, entitled“ADAPTIVE SIGMA-DELTA MODULATION WITH IMPROVED DYNAMIC RANGE,” whichapplication claims priority to co-pending and commonly-assigned U.S.Provisional Patent Application Ser. No. 60/218,103, filed on Jul. 13,2000, by Mansour A. Aldajani and Ali H. Sayed, entitled “STRUCTURE FORADAPTIVE SIGMA-DELTA MODULATION WITH IMPROVED DYNAMIC RANGE,” all ofwhich applications are incorporated by reference herein.

This application is a continuation-in-part of co-pending andcommonly-assigned U.S. patent application Ser. No. 10/256,606, entitled“CLOSED LOOP POWER CONTROL TECHNIQUES,” filed on Sep. 27, 2002, byMansour A. Aldajani and Ali H. Sayed, which application claims thebenefit under 35 U.S.C. §119(e) of the following co-pending andcommonly-assigned U.S. Provisional Patent Application Ser. No.60/325,350, entitled “CLOSED LOOP POWER CONTROL TECHNIQUES IN WIRELESSSYSTEMS,” filed on Sep. 27, 2001, by Mansour A. Aldajani and Ali H.Sayed, both of which applications are incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to analog-to-digital converters, and inparticular, to a structure for adaptive multi-bit delta and sigma-deltamodulation.

2. Description of the Related Art

(Note: This application references a number of different publications asindicated throughout the specification by reference numbers enclosed inbrackets, e.g., [x]. A list of these different publications orderedaccording to these reference numbers can be found below in the Sectionentitled “Publications” in the Detailed Description of the PreferredEmbodiment. Each of these publications is incorporated by referenceherein.)

The signal-to-noise (SNR) performance of the source coder varies withthe strength of the input signal. In pulse code modulation (PCM), forexample, the SNR is proportional to the ratio V/σ_(x) where V is thefull scale amplitude of the coder and σ_(x) is the standard deviation ofthe input signal. Waveform coders are also expected to have good dynamicrange performance, i.e., to have high SNR even for small input strength.It is well-known that log-PCM (e.g., μ-law and A-law PCM) improves thedynamic range of the coder by reducing, but not eliminating, thedependence of SNR on the ratio V/σ_(x). Another method to increase thedynamic range of coders is to use adaptive delta modulation (ADM) andadaptive sigma-delta modulation (ASDM) systems. See, for example [1]-[6]for overviews on data converters and their applications. Still,conventional ADM and ASDM systems tend to be one-bit coders and theirperformance is therefore limited by this fact.

In previous works [7, 8], two adaptive delta and sigma-delta modulationschemes have been proposed. While these schemes still employ single-bitquantization, they were nevertheless shown to exhibit superior trackingperformance, high dynamic range and improved SNR compared to othersimilar schemes. Of course, one way to further improve their performancewould be to increase the number of quantization bits.

Doing so will decrease quantization noise and increase the overall SNR.However, in the process of this modification it is useful to make adistinction between quantization bits inside a main loop of a modulatorand quantization bits inside an adapter that is used to adapt thestep-size of the modulator. The present invention maintains thequantization within the main loop to one bit, but increases thequantization within the adapter to multiple bits in a manner thatresults in improved performance.

Specifically, the present invention describes adapters using multi-bitmodulation, including a companded differential pulse code modulator, anadaptive sigma-delta modulator, an adaptive delta modulator, andadaptive differential pulse code modulation. The present invention alsodescribes a framework for studying the performance of these adapters byshowing how they can modeled in terms of first-order random gain models.Performance measures are derived from these simplified models andsimulation results are then used to illustrate a good match betweentheory and practice.

SUMMARY OF THE INVENTION

To overcome the limitations in the prior art described above, and toovercome other limitations that will become apparent upon reading andunderstanding the present specification, the present invention disclosesan adaptive multi-bit delta and sigma-delta modulation and demodulationtechnique, wherein a one-bit modulator generates a binary output signalfrom an analog input signal and a multi-bit adapter generates a signalfor scaling a step-size of the modulator.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring now to the drawings in which like reference numbers representcorresponding parts throughout:

FIG. 1A illustrates a structure for adaptive sigma delta modulation andFIG. 1B illustrates a structure for adaptive sigma delta demodulation;

FIG. 2 illustrates a structure of the adapter used for adapting thequantizer step-size;

FIG. 3 illustrates an equivalent structure of the adapter in terms of acompanded delta modulator;

FIG. 4 illustrates an adapter with a companded differential pulse-codedmodulater (DPCM) structure;

FIG. 5 illustrates a companded DPCM coder;

FIG. 6A illustrates a first-order DPCM structure and FIG. 6B illustratesa linearized DPCM structure;

FIG. 7 is a graph that shows the output of the companded DPCM codertracking an input speech signal;

FIG. 8 is a graph that shows the SNR performance of the companded DPCMcoder compared to other two schemes (B=[2-5]);

FIG. 9 is a graph that shows a comparison of theoretical and simulatedSNR for the companded DPCM coder;

FIG. 10 illustrates a structure for multi-bit adaptive sigma-deltamodulation;

FIG. 11 is a graph that shows a linearized random-gain model for themulti-bit adaptive sigma delta modulator;

FIG. 12 is a graph that shows the SNR performance of the multi-bit ASDMover input level for B=2-5;

FIG. 13 is a graph that shows the SNR dependence of the multi-bit ASDMon the oversampling ratio R for B={3,4,5} bits;

FIG. 14 is a graph that shows the effect of increasing the order of theNSF on the SNR of the multi-bit ASDM;

FIG. 15 is a graph that shows a comparison between SNR values resultingfrom theory and simulation for different bits for the multi-bit ASDM;

FIG. 16 is a graph that shows the theoretical SNR versus number of bitsfor the multi-bit ASDM;

FIG. 17 illustrates a structure for single-bit adaptive deltamodulation;

FIG. 18 illustrates a structure of an adaptive differential pulse codemodulator (ADPCM) coder;

FIG. 19 is a graph that shows the SNR performance of five coding schemeswith different attenuation factors for B=3; and

FIG. 20 is a graph that shows the SNR of the ADPCM coder versus samplingrate for different values of B.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

In the following description, reference is made to the accompanyingdrawings which form a part hereof, and which show, by way ofillustration, a preferred embodiment of the present invention. It isunderstood that other embodiments may be utilized and structural changesmay be made without departing from the scope of the present invention.

1 Overview

The present invention discloses adaptive delta and sigma-deltamodulation structures using a single quantization bit inside a main loopof a modulator and multiple quantization bits inside an adapter that isused to adapt the step-size of the modulator. Four structures where theadapter is implemented are described, including: (1) a compandeddifferential pulse code modulator, (2) an adaptive sigma-deltamodulator, and (3) an adaptive delta modulator, (4) an adaptivedifferential pulse code modulator (ADPCM). The present invention alsodescribes a framework for studying the performance of the proposedadapter structures in terms of first-order random gain models, and showthat the proposed adapter structures result in improved SNR, tracking,and high dynamic range.

2 Companded Differential Pulse Code Modulator (DPCM)

FIG. 1A illustrates the structure of a sigma-delta modulator 10 firstproposed in [7], wherein the modulator 10 is comprised mainly of twoparts: a conventional sigma-delta modulation part, and a step-sizeadaptation part.

The sigma-delta modulation part includes a summing junction 12,integrator 14 and one-bit quantizer 16, wherein the difference between asampled analog input signal x(n) and an output signal p(n) from theintegrater 14 is converted into a binary output signal y(n) having aspecified number of bits at the quantizer 16. The binary output signaly(n) is a representation of the analog input signal x(n) contaminatedwith noise created by the quantizer 16.

The step-size adaptation part includes an absolute value block 20,digital-to-analog converter (DAC) 22, adapter 24, multiplier 26 anddelay 28, wherein the step-size of the quantizer 16 is adapted based onestimates of absolute value of the signal p(n), where p(n) is the inputto the quantizer 16. The absolute value block 20 generates the absolutevalue signal |p(n)| to the quantizer 16. The DAC 22 converts the outputy(n) from the quantizer 16. The adapter 24 uses the absolute valuesignal |p(n)| output from the absolute value block 20 to produce ascaling signal d(n), which is an approximation of the absolute valuesignal |p(n)|, and a binary sequence signal q(n) from which the signald(n) can be re-generated. The scaling signal d(n) is multiplied by themultiplier 26 using the output y(n) from the DAC 20 to create an encodedsignal v(n):v(n)=y(n)d(n)

The encoded signal v(n) is delayed at the delay 28 and the delayedsignal v(n−1) is subtracted from the analog input signal x(n) at thesumming junction 12 to generate an error signal e_(a)(n):e _(a)(n)=x(n)−v(n−1)

The error signal e_(a)(n) is then passed through the integrator 14, andthe signal p(n) is output from the integrator 14. The signal p(n) isquantized by the quantizer 16 to produce the binary output signal y(n).

FIG. 1B illustrates the structure of a sigma-delta demodulator 30,wherein the demodulator 30 is also comprised mainly of two parts: asigma-delta demodulation part, and a step-size adaptation part. Thesigma-delta demodulation part is similar in function to the sigma-deltamodulation described in conjunction with FIG. 1A, and includes a lowpass filter 32 that filters out a shaped quantization signal from thebinary output signal y(n), thereby resulting in an approximation({circumflex over (x)}(n)) of the original analog input signal x(n).Similar to the modulator 10, the step-size adaptation part includes amultiplier 34 and adapter 24, wherein the adapter 24 accepts the signalq(n) from the modulator 10 and generates the scaling signal d(n) to varythe step-size of the demodulater 30.

The key difference in relation to other sigma-delta modulators is in themanner by which the adapter 24 functions. The functionality of theadapter 24 is illustrated in FIG. 2.

The adapter 24 includes a summing junction 12, one-bit quantizer 16,integrator 14, delay 28 and exponential term block 36. A delayed scalingsignal d(n−1) is subtracted from the absolute value of the signal p(n)at summing junction 12, and the results therefrom are quantized by thequantized 16. The binary sequence signal q(n), from which the signald(n) can be re-generated, is output by the quantizer 16 to theintegrater 14, which generates the signal w(n) as an input to theexponential term block 36. The exponential term block 36 outputs thescaling signal d(n), which is output from the adapter 24, and also inputto the delay 28 to create the delayed scaling signal d(n−1).

The purpose of the adapter 24 is to adapt the step-size of the quantizer16 and, as can be seen from the figure, the adapter 24 functions as adelta modulator in its own right with an additional exponential termblock 36. The purpose of this additional exponential term block 36 is toboost up the tracking performance of the adapter 24. This adapter 24differs from other adaptation schemes (e.g., [9]-[11]) in that it usesthe input signal |p(n)| rather than the original input signal x(n)itself. The result is an increase in both SNR and dynamic range incomparison to conventional SDMs. In particular, the analysis in [7]showed that the SNR of the system is independent of the input strength.

Actually, the analysis in [7] further showed that the adapter 24 of FIG.2 could be redrawn in an equivalent form as a companded delta modulator38, as shown in FIG. 3. The companded delta modulator 38 includes alogarithm term block 40, delta modulator (DM) 42 and exponential termblock 36, wherein the input signal to the companded delta modulator 38is |p(n)| and the output signal from the companded delta modulator 38 isd(n). The mapping from |p(n)| to d(n) undergoes companding at 40 andexpansion at 36 in addition to delta modulation at 38. This equivalentstructure is very useful, since it suggests a way to extend thedesirable properties of the single-bit ASDM of [7] to the multi-bitscenario.

First, the DM 42 inside the adapter 24 may be replaced by a more genericdifferential pulse code modulator (DPCM) as shown in FIG. 4. The adapter24 of FIG. 4 includes a logarithm term block 44 for companding thesignal |p(n)| to recreate an analog signal x_(d)(n), an op-amp 46 foradjusting the signal x_(d)(n) by a scaling factor 1/S, a DPCM 48 fordifferentially pulse code modulating the adjusted x_(d)(n) to generate abinary output signal y_(d)(n), an op-amp 50 for adjusting the binaryoutput signal y_(d)(n) by a scaling factor S, and an exponential termblock 36 for expanding the adjusted y_(d)(n) to generate a delayedscaling factor d(n−1). In parallel, the signal |p(n)| is quantized by aone-bit quantizer 16 to generate a binary output signal y(n), whereiny(n) is multiplied at multiplier 26 by the delayed scaling factor d(n−1)to generate a encoded signal v(n). Note that in this structure, whereinthe input signal to the adapter 24 is |p(n)| and the output signal fromthe adapter 24 is v(n).

The motivation behind this extension is that the DM 42 is a special caseof DPCM 48, wherein the DPCM 48 uses multi-bit quantization andhigher-order prediction (it is sufficient to assume a single delaypredictor) and results in better coding. Therefore, using the DPCM 48 inthe adapter 28 instead of a DM 42 should improve the trackingperformance of the adapter 24.

The scaling factor 1/S of op-amp 46 adds flexibility and improvestracking performance for the adapter 24. Moreover, the range of theinput to the DPCM 48 can be adjusted by tuning S.

Of course, the companded DPCM adapter 24 can also function as astand-alone coder as well. For this reason, and for generality, thestructure of FIG. 4 can redrawn as shown in FIG. 5, and its input signaldenoted more generically by x(n) instead of |p(n)|.

The following describes the performance of the companded DPCM system,and the resulting multi-bit ASDM. Among other results, expressions forthe mean and variance of the coding error are derived, as well as anexpression for the SNR of the overall system. These results will beachieved by first showing how the companded system can be modeled as asingle random gain with known statistics.

2.1 Random Gain Model

To begin with, from FIG. 5, the input to the DPCM 48, x_(d)(n), is givenby:

$\begin{matrix}{{x_{d}(n)} = {\frac{1}{S}\log_{\alpha}{{x(n)}}}} & (1)\end{matrix}$

where x(n) is the input signal to the coder. The output of the DPCM 48,denoted by y_(d)(n), is multiplied by the scaling factor S at op-amp 50and then decompressed by the exponential term block 36 to give:d(n)=α^(Sy) ^(d) ^((n))  (2)and:v(n)=y(n)d(n)  (3)

where y(n) is the sign of x(n).

The objective in this section is to show that the input-output mappingof the companded DPCM 48 of FIG. 5 (i.e., from x(n) to v(n)) can bemodeled as:v(n)=K(n)x(n)

for some random gain K(n) that is going to be characterized. Thisintermediate result will be very useful in characterizing theperformance of the overall companded DPCM and multi-bit ASDM structures.

FIG. 6A illustrates the structure of the original DPCM 48. The DPCM 48of FIG. 6A includes a summing junction 12, multi-bit quantizer 52,integrator 14 and delay 28, wherein the input signal to the DPCM 48 isx_(d)(n) and the output signal from the DPCM 48 is y_(d)(n).

FIG. 6B illustrates a linearized version of the DPCM 48. The DPCM 48 ofFIG. 6B is similar to FIG. 6A except that the multi-bit quantizer 52 isreplaced by a summing junction 12 for an additive quanitization errore_(d)(n)

The additive quantization error e_(d)(n) is assumed to be uniform withinthe interval:

$\left\lbrack {{- \frac{\Delta}{2}},\frac{\Delta}{2}} \right\rbrack$

where Δ=2/2^(B) and B is the number of bits of the coder (B−1 bits aredevoted to the quantizer 16 and the remaining bit carries the signsignal). The quantization error is further assumed to be independent ofall other variables.

In the z-transform domain, the operation of the linearized DPCM 48 isdescribed by:

${Y_{d}(z)} = {\frac{\frac{1}{1 - z^{- 1}}}{1 + \frac{z^{- 1}}{1 - z^{- 1}}}\left( {{X_{d}(z)} + {E_{d}(z)}} \right)}$

which simplifies to:Y _(d)(z)=X _(d)(z)+E _(d)(z)

In other words:y _(d)(n)=x _(d)(n)+e _(d)(n)

so that using equation (1) results in:

${y_{d}(n)} = {{\frac{1}{S}\log_{\alpha}{{x(n)}}} + {e_{d}(n)}}$

Substituting back into (2):

${d(n)} = \alpha^{S{({{\frac{1}{S}\log_{\alpha}{{x{(n)}}}} + {e_{d}{(n)}}})}}$

This equation can be simplified to:d(n)=|x(n)|α^(Se) ^(d) ^((n))Now, since:v(n)=y(n)d(n)then:v(n)=x(n)e ^(Se) ^(d) ^((n))

Finally, if the following is defined:

$\begin{matrix}{{K(n)}\overset{\bigtriangleup}{=}\alpha^{{Se}_{d}{(n)}}} & (3)\end{matrix}$

the desired relation is:v(n)=K(n)x(n)  (4)

This result shows that the companded DPCM coder of FIG. 6B can bemodeled by a single random gain K(n), which is a function of S ande_(d)(n) only. In the sequel, it is assumed that all random processesare stationary.

2.2 Signal-to-Noise (SNR) Performance

Now it is easy to verify that the first and second moments of K(n) aregiven by:

$\begin{matrix}{E_{K}\overset{\bigtriangleup}{=}{{E\left\{ K \right\}} = {\int_{- \frac{\Delta}{2}}^{\frac{\Delta}{2}}{\frac{1}{\Delta}\alpha^{S\eta}\ {\mathbb{d}\eta}}}}} \\{= {\frac{1}{\Delta\; S\;{\ln(\alpha)}}\left( {\alpha^{S\;{\Delta/2}} - \alpha^{{{- S}\;{\Delta/2}}\;}} \right)}}\end{matrix}$ and: $\begin{matrix}{E_{K^{2}}\overset{\bigtriangleup}{=}{{E\left\{ K^{2} \right\}} = {\int_{- \frac{\Delta}{2}}^{\frac{\Delta}{2}}{\frac{1}{\Delta}\alpha^{2{S\eta}_{d\;\eta}}}}}} \\{= {\frac{1}{2\Delta\; S\;{\ln(\alpha)}}\left( {\alpha^{S\;\Delta} - \alpha^{{{- S}\;\Delta}\;}} \right)}}\end{matrix}$

Let e_(c)(n) denote the coding error:e _(c)(n)=x(n)−v(n)  (5)

The above results allow an expression for the expected value andvariance of e_(c)(n) to be derived. To see this, the expected value ofboth sides of (4) is evaluated:E{v(n)}=E{K(n)x(n)}  (6)and the independence of {e_(d)(n)} with all other variables is invokedto conclude that:E _(v) =E _(K) E _(x)and, therefore:E _(e) _(c) =(1−E _(K))E _(x)  (7)

Here, the notations {E_(v), E_(x), E_(e) _(c) } are used to denote themeans {v(n), x(n), e_(c)(n)}, respectively.

Moreover, by squaring both sides of the error expression (5), thefollowing is obtained:e _(c) ²(n)=x ²(n)−2x(n)v(n)+v ²(n)

Taking the expected value of both sides, it is found that:E _(e) _(c) ₂ =E _(x) ₂ −2E _(xv) +E _(v) ₂Now since:E_(xv) =E{K(n)x ²(n)}=E _(K) E _(X) ₂and:E _(v) ₂ =E{K ²(n)x ²(n)}=E _(K) ₂ E _(x) ₂results in:E _(e) _(c) ₂ =E _(x) ₂ −2E _(K) E _(x) ₂ +E _(K) ₂ E _(x) ₂

In other words:E _(e) _(c) ₂ =(1−2E _(K) +E _(K) ₂ )E _(x) ₂   (8)

The variance of the coding error is:σ_(e) _(c) ² ΔE _(e) _(c) ₂ −(E _(e) _(c) )²

and from (7) and (8) the following is obtained:σ_(e) _(c) ²=(1−2E _(K) +E _(K) ₂ )E _(x) ₂ −(1−E _(K))² E _(x) ²  (9)

Finally, in computing the SNR, it is assumed that the input signal iszero mean (so that σ_(e) _(c) ²=E_(e) _(c) ₂ ) Therefore, equation (9)can be rewritten as:σ_(e) _(c) ²=(1−2E _(K) +E _(K) ₂ )σ_(x) ²  (10)

The SNR is defined as SNR=σ_(x) ²/σ_(e) _(c) ². Using equation (10), thevariance of the input signal σ² _(x) will cancel out, leading to thefollowing expression:

$\begin{matrix}{{SNR} = \frac{1}{1 - {2E_{K}} + E_{K^{2}}}} & (11)\end{matrix}$

The theoretical SNR is therefore independent of the input strength. Insummary, the following result is obtained:

Theorem 1: SNR of the Companded DPCM. For the companded DPCM coder ofFIG. 5, the coding error e_(c)(n)=x(n)−v(n) has zero mean and variance:

$\begin{matrix}{{\sigma_{e_{c}}^{2} = {\left( {1 - {2E_{K}} + E_{K^{2}}} \right)\sigma_{x}^{2}}}{\text{where}\text{:}}{E_{K} = {\frac{1}{\Delta\; S\;{\ln(\alpha)}}\left( {\alpha^{S\;{\Delta/2}} - \alpha^{{- S}\;{\Delta/2}}} \right)}}} \\{E_{K^{2}} = {\frac{1}{2\Delta\; S\;{\ln(\alpha)}}\left( {\alpha^{S\;\Delta} - \alpha^{{- S}\;\Delta}} \right)}}\end{matrix}$and σ_(x) ² is the variance of the input x(n). The constants Δ, S, and αare the quantizer step-size, the scaling factor of the DPCM input, andthe exponent term, respectively. Furthermore, the SNR of this coder isindependent of the input strength and given by:

${SNR} = \frac{1}{1 - {2E_{K}} + E_{K^{2}}}$

2.3 Simulations

The companded DPCM coder was simulated using Matlab. FIG. 7 shows theoutput v(ii) tracking a speech input sampled at F_(s)=22 kHz. Theexponent term α, the scaling factor S, and the number of bits B arechosen as 1.25, 5, and 4, respectively. The figure shows a closetracking even at high variations in the speech signal.

Next, the dynamic range of the coder was investigated. In this test, theinput signal is attentuated by a factor κ and then run through thecoder. The resulting SNR of the coder was measured. A different value ofκ was chosen and the process was repeated. FIG. 8 shows the resultingSNR versus the attenuation factor κ together with that obtained usingμ-law PCM and A-law PCM for B=[2-5]. The proposed coder demonstrateshigher SNR performance than the other two coders. Furthermore, theproposed coder shows almost flat SNR performance over input strengthoutperforming the other two coders and resulting in a noticeably higherdynamic range.

FIG. 9 shows a comparison between the theoretical SNR derived earlier,in equation (11), and the simulated SNR for B=[2-5]. A sine waveforminput was used in this simulation and the scaling factor S was chosen tobe unity. The figure shows a close match between the two quantities.

3 Multi-Bit Adaptive Sigma-Delta Modulation (ASDM)

As explained before, besides functioning as a stand-alone coder, thecompanded DPCM 48 of FIG. 5, with x(n) replaced by p(n) as in FIG. 4,can be used to adapt the step-size of the ASDM of FIG. 1. The resultingstructure is shown in FIG. 10. The main loop is a conventionalsingle-bit SDM with a noise shaping filter H(z) 54. The results of theprevious section can then be used to characterize the performance of theresulting ASDM structure.

3.1 SNR Performance

Section 2 above showed that the input-output mapping of the compandedDPCM 48 can be modeled as the random gain 56, having a value K(n)=α^(Se)^(d) ^((n)), where e_(d)(n) is the quantization error associated withthe quantizer 16. Therefore, the functionality of the multi-bit ASDMstructure can be modeled as shown in FIG. 11. The difference betweenthis model and the one developed in [7] for the single-bit case lies inthe values of the first and second-order moments of gain K(n) 56. In themulti-bit case, as can be seen from the statement of Theorem 1, thesemoments depend on S and the value of Δ is now smaller.

Therefore, the derivation carried out in the single-bit case in [7] canbe extended rather directly to the multi-bit case resulting in thefollowing SNR expression for the multi-bit ASDM system:

$\begin{matrix}{{SNR} = \frac{R}{\left( {1 - {2\Gamma\; A^{- 1}1}} \right)\left( {{\psi\mspace{11mu} E_{K^{2}}} - 1} \right)}} & (12)\end{matrix}$where the quantities {A, Γ, 1, ψ, R} are defined as follows:

$\begin{matrix}{\beta = \frac{1}{E_{K}}} \\{A = {\begin{pmatrix}{1 + \beta} & 1 & 1 & \ldots & 1 \\2 & {1 + \beta} & 1 & \ldots & 1 \\2 & 2 & {1 + \beta} & \ldots & 1 \\\vdots & \vdots & \vdots & \ldots & \vdots \\2 & 2 & 2 & \ldots & {1 + \beta}\end{pmatrix}\left( {M \times M} \right)}} \\{\Gamma = {\left\lbrack {\frac{\sin\left( \omega_{B} \right)}{\omega_{B}}\frac{\sin\left( {2\omega_{B}} \right)}{2\omega_{B}}\mspace{11mu}\ldots\mspace{11mu}\frac{\sin\left( {M\;\omega_{B}} \right)}{M\;\omega_{B}}} \right\rbrack\left( {1 \times M} \right)}} \\{1 = {\left\lbrack {1\mspace{14mu} 1\mspace{14mu} 1\mspace{11mu}\ldots\mspace{14mu} 1} \right\rbrack^{T}\left( {M \times 1} \right)}} \\{\psi = \frac{2 - E_{K}}{E_{K}\left( {{2E_{K}} - E_{K^{2}}} \right)}}\end{matrix}$

The constant R is the oversampling ratio (OSR) and ω_(B) is thebandwidth of the input signal in radians/sec. The matrix size M is aninteger approximation of the span of the autocorrelation function of themodulation error. A typical value for M is between 4 and 10. Thus,observe again that the theoretical SNR is independent of the inputsignal strength.

3.2 Simulations

The multi-bit ASDM was simulated using Matlab with a sinusoidal input.The parameters α, S, and the oversampling ratio (R) were chosen as 2.2,1, and 64, respectively. FIG. 12 shows the SNR performance of theproposed modulator for B=2-5 bits. From these figures, the following canbe observed. First, the SNR shows a flat response over input levelsupporting the, theoretical findings. Second, the SNR increases by anaverage of 6 dB with 1-bit increase in the quantizer. FIG. 13 shows theSNR dependence on the oversampling ratio R for B=3-6 bits at −5 dB inputamplitude. The plot also includes the performance of the conventionalSDM for the sake of comparison.

In another test, the effect of increasing the order of the noise shapingfilter (NSF) H(z) on the performance of the modulator was investigated.FIG. 14 shows the SNR versus the input level for B=3-4 and for 1st and2nd order NSF. The figure shows an improvement of up to 14 dB in SNRwhen B=3 bits and up to 24 dB improvement when B=4 bits.

The expression for SNR shown in (12) was tested by comparing it withsimulation results. FIG. 15 shows a comparison between the theoreticaland simulated SNR for a sinusoidal input with R=64, S=1, α=1.95, andB=[3, 6]. The plot shows a close match between theory and simulations.

Finally, the theoretical SNR is plotted against the number of bits B ofthe overall modulator. The result is shown in FIG. 16. The SNR increasesby 6 dB as a result of increasing the number of bits by one.

It may be remarked that since ASDM implementation employs analogcircuitry, circuit noise becomes a limiting factor such as noisegenerated by the ADC nonlinearity and thermal noise. While these arerelevant issues, the focus in this application is on modeling andstudying the performance of the proposed structures.

4 Adaptive Differential Pulse Code Modulation (LPCM)

In a related work [8], a structure for adaptive delta (as opposed tosigma-delta) modulation with improved tracking performance was alsoproposed. The modulator is shown in FIG. 17 and its operation isdescribed by the equations:e _(a)(n)=x(n)−v(n−1)q(n)=sign[|e_(a)(n)|−d(n−1)]d(n)=α^(q(n))v(n)=v(n−1)+sign[e _(a)(n)]d(n)

Again, the key difference in relation to other adaptive delta modulators(e.g., [12]-[13]) is that the adaptation procedure uses the input to thequantizer rather than the original input itself.

First, the following variables are introduced:

${x_{d}(n)}\overset{\Delta}{=}{\log_{\alpha}\left( {{p(n)}} \right)}$${y_{d}(n)}\overset{\Delta}{=}{\log_{\alpha}\left( {d(n)} \right)}$

Observe again that the adaptation scheme in the upper branch of thefigure amounts to delta modulation as well. Therefore, an extension tothe multi-bit case can again be obtained by replacing the DM adaptivescheme with the companded DPCM 58 shown in FIG. 18. The resultingstructure is referred to as an ADPCM system. It will be seen in thissection that this structure maintains the same high dynamic rangeperformance of the ADM and log-DPCM structures and also has improvedSNR.

4.1 Performance

From the discussions in the previous sections it is already known thatthe following can be written:

$\begin{matrix}{{{v(n)} = {{K(n)}{x(n)}}}{\;{where}\text{:}}} & (13) \\{{K(n)}\overset{\Delta}{=}\alpha^{{Se}_{d}{(n)}}} & (14)\end{matrix}$

In other words, the companded DPCM part of this coder can be replaced bythe random gain K(n). Now, it was shown in [8] that the single-bit ADMcoder is BIBO stable. This conclusion can be extended to the multi-bitcase by relying on the random gain model.

Thus, note that, since:v(n)=(1−K(n))v(n−1)+K(n)x(n)

the following is obtained:

${v(n)} = {\sum\limits_{i = 1}^{n}\;{\prod\limits_{j = i}^{n}\;{\left( {1 - {K(j)}} \right){K(i)}{x(i)}}}}$

If the input signal x(n) has a bound Λ, then:|K(n)x(n)|≦Λ|K(n)|  (15)

and using an analysis similar to the single-bit case from [8], it can beverified that if α is chosen in the open interval:

$\begin{matrix}{2^{\frac{2}{S\;\Delta}} < \alpha < 2^{\frac{2}{S\;\Delta}}} & (16)\end{matrix}$then a bound L can be found such that:|1−K(n)|≦L<1

Using this result, the following can then be written:

$\begin{matrix}{{{v(n)}} \leq {\alpha^{S\;{\Delta/2}}\Lambda{\sum\limits_{i = 1}^{n}\; L^{j}}}} & (17)\end{matrix}$

and it can be concluded that the modulator output is bounded by:

${{v(n)}} \leq {\alpha^{S\;{\Delta/2}}\Lambda\frac{L}{1 - L}}$

so that the modulator is BIBO stable under the sufficient condition(16).

4.2 Simulations

The performance of the ADPCM coder was tested via simulations. A speechwaveform was coded at a bit rate of 32 kHz using the proposed coder. Theparameters α and S were chosen as 1.8 and 5, respectively. The SNR wasused as a qualitative measure of the quality of the decoded speech. Inorder to test the dynamic range of the coder, the same experiment wasconducted as in the DPCM case. Different attenuation factors K wereapplied to the input speech and the SNR was measured for each value ofK. The result is shown in FIG. 19 with B=3 together with that obtainedusing PCM and μ-law PCM for the sake of comparison. Unlike otherschemes, the SNR obtained by the proposed coder is independent of theinput strength with improvement of about 9 dB over μ-law PCM.

In a different experiment, the effect of the input sampling rate on theperformance of the coder was investigated. FIG. 20 shows the SNRperformance versus sampling rate of the input speech at different numberof bits. The SNR changes approximately in a linear fashion with respectto the sampling rate.

5 References

The following references are incorporated by reference herein:

-   -   [1] Owen, F., PCM and Digital Transmission Systems, McGraw-Hill        Book Company, New York, 1982.    -   [2] S. Hein and A. Zakhor, Sigma Delta Modulators, Nonlinear        Decoding Algorithms and Stability Analysis, Kluwer Academic        Publishers, MA, 1993.    -   [3] S. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data        Converters, IEEE Circuits and Systems Society, IEEE Press, NJ,        1997.    -   [4] Proakis, J., Digital Communications, McGraw-Hill Higher        Education, NY, 2001.    -   [5] L. Robiner and R. Schafer, Digital Processing of Speech        Signals, Prentice-Hall, NJ, 1978.    -   [6] P. Aziz, H. Sorensen, and J. Spiegel, “An overview of        sigma-delta converters,” IEEE Signal Processing Magazine, vol.        13, no. 1, pp. 61-84, January 1996.    -   [7] M. A. Aldajani and A. H. Sayed, “Stability and performance        analysis of an adaptive sigma-delta modulator,” IEEE Trans. on        Circuits and Systems II: Analog and Digital Signal Processing,        vol. 48, no. 3, pp. 233-44, March 2001.    -   [8] M. A. Aldajani and A. H. Sayed, “A stable adaptive structure        for delta modulation with improved performance,” Proc.        International Conference on Acoustics, Speech, and Signal        Processing, vol. IV, Salt Lake City, Utah, May 2001.    -   [9] J. Yu, M. Sandler, and R. Hwaken, “Adaptive quantization for        one bit delta sigma modulation,” IEEE Proceedings G (Circuits,        Devices and Systems), vol. 139, no. 1, pp. 39-44, February 1992.    -   [10] C. Dunn and M. Sandler, “Fixed and adaptive sigma-delta        modulator with multibit quantizers,” Applied signal processing,        vol. 3, no. 4, pp. 212-222, 1996.    -   [11] M. Ramesh and K. Chao, “Sigma delta analog to digital        converters with adaptive quantization,” Proceedings of Midwest        Symposium on Circuits and Systems, vol. 1.2, pp. 22-25, 1998.    -   [12] C. Chakravarthy, “An amplitude controlled adaptive delta        sigma modulators,” Radio and Electronic Engineering, vol. 49,        no. 1, pp. 49-54, January 1979.    -   [13] M. Jaggi and C. Chakravarthy, “Instantaneous adaptive delta        sigma modulator,” Canadian Electrical Engineering Journal, vol.        11, no. 1, pp. 3-6, January 1986.

6 Conclusion

In conclusion, the present invention discloses adaptive delta andsigma-delta modulation structures using a single quantization bit insidea main loop of a modulator and multiple quantization bits inside anadapter that is used to adapt the step-size of the modulator. Fourapplications where the adapter is implemented were described, including:(1) a companded differential pulse code modulator, (2) an adaptivesigma-delta modulator, (3) an adaptive delta modulator, (4) an adaptivedifferential pulse code modulator (ADPCM). The present invention alsodescribes a framework for studying the performance of the proposedadapter structures in terms of first-order random gain models, and showthat the proposed adaptive modulation structures result in improved SNR,tracking, and high dynamic range.

This concludes the description including the preferred embodiments ofthe present invention. The foregoing description of the preferredembodiment of the invention has been presented for the purposes ofillustration and description. It is not intended to be exhaustive or tolimit the invention to the precise form disclosed. Many modificationsand variations are possible in light of the above teaching.

It is intended that the scope of the invention be limited not by thisdetailed description, but rather by the claims appended hereto. Theabove specification, examples and data provide a complete description ofthe manufacture and use of the composition of the invention. Since manyembodiments of the invention can be made without departing from thespirit and scope of the invention, the invention resides in the claimshereinafter appended.

1. An apparatus for adaptive modulation, comprising: a one-bit modulator, including a quantizer, for generating a binary output signal from an analog input signal using a single quantization bit; and a multi-bit adapter for generating a scaling signal for scaling a step-size of the modulator using multiple quantization bits, wherein the step-size is adapted based on an estimate of an absolute value of a signal output from a filter before the signal is input to the quantizer.
 2. The apparatus of claim 1, wherein the adapter includes a companded differential pulse code modulator (DPCM).
 3. The apparatus of claim 2, wherein the adapter includes a logarithm term block for companding an absolute value of a filtered error signal, the companded DPCM for modulating an output of the logarithm term block, and an exponential term block for expanding an output of the companded DPCM.
 4. The apparatus of claim 1, wherein the modulator comprising: a summing junction for comparing an analog input signal x(n) to an encoding signal v(n) to generate an error signal e(n) representing a difference between the analog input signal x(n) and the encoding signal v(n); the filter for filtering the error signal e(n) to generate a signal p(n); the quantizer for converting the signal p(n) into a binary output signal y(n); a multiplier for multiplying the binary output signal y(n) by a scaling signal d(n) output by the adapter to generate the encoding signal v(n); and a delay for delaying the encoding signal v(n) to generate a delayed encoding signal v(n−1).
 5. The apparatus of claim 4, wherein the adapter produces both the scaling signal d(n), which is an approximation of the absolute value of the signal p(n), and a binary sequence signal q(n) from which the scaling signal d(n) can be re-generated.
 6. The apparatus of claim 1, wherein the adapter is used in an adaptive sigma-delta modulator.
 7. The apparatus of claim 1, wherein the adapter is used in an adaptive delta modulator.
 8. The apparatus of claim 1, wherein the adapter is used as a companded delta modulator.
 9. An apparatus for adaptive demodulation, comprising: a multi-bit adapter for receiving a binary sequence signal q(n) from an adapter of an adaptive modulation apparatus and for generating a scaling signal d(n) in response thereto using multiple quantization bits; a multiplier for multiplying a binary output signal y(n) received from a one bit modulator of the adaptive modulation apparatus by the scaling signal d(n) to generate an encoding signal v(n), wherein the binary output signal y(n) is generated by the one-bit modulator from an analog input signal x(n) using a single quantization bit; and a low-pass filter for receiving the encoding signal v(n) and for generating a signal {circumflex over (x)}(n), which is a re-creation of the analog input signal x(n) to the modulator of the adaptive modulation apparatus; wherein the binary sequence signal q(n) is generated by the adapter of the adaptive modulation apparatus based on an estimate of an absolute value of signal output from a filter before the signal is input to a quantizer in the one bit modulator of the adaptive modulation apparatus.
 10. The apparatus of claim 9, wherein the adapter includes a companded differential pulse code modulator (DPCM).
 11. The apparatus of claim 10, wherein the adapter includes a logarithm term block for companding an absolute value of a filtered error signal, the companded DPCM for modulating an output of the logarithm term block, and an exponential term block for expanding an output of the companded DPCM.
 12. The apparatus of claim 9, wherein the adapter is used in an adaptive sigma-delta modulator.
 13. The apparatus of claim 9, wherein the adapter is used in an adaptive delta modulator.
 14. The apparatus of claim 9, wherein the adapter is used as a companded delta modulator. 